DSPIC30F6013T-20I/PF【PDF 51/228 页】IC DSPIC MCU/DSP 132K 80TQFP

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dsPIC30F6011/6012/6013/6014

DS70117F-page 142

2006 Microchip Technology Inc.

19.9

Module Power-down Modes

The module has 2 internal Power modes.

When the ADON bit is ‘1’, the module is in Active mode;

it is fully powered and functional.

When ADON is ‘0’, the module is in Off mode. The dig-

ital and analog portions of the circuit are disabled for

maximum current savings.

In order to return to the Active mode from Off mode, the

user must wait for the ADC circuitry to stabilize.

19.10 ADC Operation During CPU Sleep

and Idle Modes

19.10.1

ADC OPERATION DURING CPU

SLEEP MODE

When the device enters Sleep mode, all clock sources

to the module are shutdown and stay at logic ‘0’.

If Sleep occurs in the middle of a conversion, the con-

version is aborted. The converter will not continue with

a partially completed conversion on exit from Sleep

mode.

entering or leaving Sleep mode.

The ADC module can operate during Sleep mode if the

ADC clock source is set to RC (ADRC = 1). When the

RC clock source is selected, the A/D module waits one

instruction cycle before starting the conversion. This

allows the SLEEP instruction to be executed which elim-

inates all digital switching noise from the conversion.

When the conversion is complete, the CONV bit will be

cleared and the result loaded into the ADCBUF register.

If the A/D interrupt is enabled, the device will wake-up

from Sleep. If the A/D interrupt is not enabled, the ADC

module will then be turned off, although the ADON bit

will remain set.

19.10.2

A/D OPERATION DURING CPU IDLE

MODE

The ADSIDL bit selects if the module will stop on Idle or

continue on Idle. If ADSIDL = 0, the module will con-

tinue operation on assertion of Idle mode. If ADSIDL =

, the module will stop on Idle.

19.11 Effects of a Reset

A device Reset forces all registers to their Reset state.

This forces the ADC module to be turned off, and any

conversion and sampling sequence is aborted. The val-

ues that are in the ADCBUF registers are not modified.

The A/D Result register will contain unknown data after

a Power-on Reset.

19.12 Output Formats

The ADC result is 12 bits wide. The data buffer RAM is

also 12 bits wide. The 12-bit data can be read in one of

four different formats. The FORM<1:0> bits select the

format. Each of the output formats translates to a 16-bit

result on the data bus.

FIGURE 19-5:

ADC OUTPUT DATA FORMATS

RAM Contents:

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Read to Bus:

Signed Fractional

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0000

Fractional

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

0000

Signed Integer

d11 d11 d11 d11 d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

Integer

0000

d11 d10 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00

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